OPERATION

This device is a high-frequency, synchronous, step-down power supply. It is available with a wide 4.5V to 36V input supply range and can achieve up to 3A continuous output current with excellent load and line regulation over an ambient temperature range of -40°C to +125°C.

PWM Control

At moderate to high output currents, this device operates in a fixed-frequency, peak current control mode to regulate the output voltage. An internal clock initiates a PWM cycle. Then the rising edge of the clock the high-side switch (HS-FET) turns on and the inductor current rises linearly to provide energy to the load. The HS-FET remains on until its current reaches the COMP voltage, which is the output of the internal error amplifier. The output voltage of error amplifier depends on the difference of output feedback voltage and the internal high-precision reference. It determines how much energy should be transferred to the load. The higher the load current, the higher the COMP voltage will be. Both the feedback divider ratio and reference can be adjusted by the I²C, which makes it easy to adjust for different output voltages.

When the HS-FET is off, the low-side switch (LS-FET) turns on immediately and remains on until the next clock starts. During this time, the inductor current flows through the LS-FET. In order to avoid shoot-through, dead time is inserted to avoid the HS-FET and LS-FET turning on at the same time.

If in one PWM period, the current in the HS-FET does not reach the COMP set current value, the HS-FET remains on, saving a turn-off operation.

Mode Selection (AAM and Forced CCM)

This device can operate in light load AAM or forced CCM mode. AAM (advanced asynchronous modulation) mode is employed to optimize the efficiency during light-load or no-load conditions. Forced CCM can maintain a constant switching frequency and smaller output ripple, but it has low efficiency at light load.

If AAM mode is enabled with load decreasing, the device enters discontinuous conduction operation (DCM) with fixed-frequency as long as the inductor current approaches zero. If the load is further decreased or there is no load that makes the inductor peak current below AAM peak current threshold set by the I²C, the device enters sleep mode. In sleep mode, it consumes very low quiescent current to further improve light-load efficiency. The internal clock is also blocked, and the device skips some pulses. The feedback voltage is less than the reference, so VCOMP ramps up until the inductor peak current exceeds the AAM threshold. Then the internal clock is reset, and the crossover time is taken as the benchmark of the next clock. This control scheme helps achieve high efficiency by scaling down the frequency to reduce switching and gate driver losses.

As the output current increases from light load, V_COMP and the switching frequency increase. If the output current exceeds the critical level set by V_COMP, the device resumes fixed-frequency PWM control.

When forced CCM is enabled, the device operates in fixed-frequency peak current control mode to regulate the output voltage, regardless of the output current.

Figure 6: A Complete Data Transfer

Internal Regulator

A 5V internal regulator powers most of the internal circuitries. This regulator takes V_IN and operates in the full V_IN range. When V_IN exceeds 5.0V, the output of the regulator is in full regulation. Lower V_IN values result in lower output voltages. The regulator is enabled when V_IN exceeds its UVLO threshold and EN is high. In EN shutdown mode, the internal VCC regulator is disabled to reduce power dissipation.

For better thermal performance, BIAS mode can be chosen via the I²C if V_OUT is greater than 5V. VCC and the internal circuit are then powered by V_OUT.

Enable Control

EN is a digital control pin that turns the regulator, including I²C block on and off. Drive EN high to turn on the regulator; drive it low to turn the regulator off. The EN threshold can be programmed by the I²C. An internal 5MΩ resistor from EN to GND allows EN to be floated to shut down the chip.

Oscillator Frequency

The default frequency of this device is 500kHz, and it can be programmed from 250kHz to 2.5MHz by the I²C. The frequency can also be set by a logic level synchronal signal.

SYNC IN and SYNC OUT

The SYNC pin can be programmed by the I²C to SYNC IN or SYNC OUT. When operating as SYNC IN, the internal oscillator frequency can be synchronized by an external clock via this pin. At start-up, the device first operates at the internal set frequency, and quickly synchronizes to the external clock once soft start is ready. Ensure the high amplitude of the SYNC clock is above 1.8V and the low amplitude is below 0.4V to drive the internal logic. The recommended external SYNC frequency is between 250kHz and 2.5MHz

The device operates in forced CCM mode with a fixed frequency when there is a SYNC clock, regardless of the output current. A pulse longer than 200ns is recommended in application.

When the SYNC pin is set to SYNC OUT, the device can output the internal clock with a 0° or 180° phase shift. By this function, two devices can operate in same frequency but 180° out of phase to reduce the total input current ripple so that a smaller input bypass capacitor can be used.

Under-Voltage Lockout (UVLO)

The device has input under-voltage lockout protection (UVLO) to ensure reliable output power. Assuming EN is active, the device is powered on when the input voltage exceeds the UVLO rising threshold, and is powered off when the input voltage drops below the UVLO falling threshold. The UVLO threshold can be set between 3.3V and 7.5V the I²C. This function prevents the device from operating at an insufficient voltage. It is a non-latch protection.

Soft-Start

The device has built-in soft start (SS), which ramps up the output voltage in a controlled slew rate when the EN pin goes high, avoiding overshoot during start-up. When the chip starts, the internal circuitry generates a soft-start voltage that ramps up slowly. When the SS voltage (VSS) is below the internal reference (VREF), VSS overrides VREF as the error amplifier reference. When VSS exceeds VREF, VREF acts as the reference. At this point, soft start finishes and the device enters steady state.

The SS time is internally set to default 1ms, and can also be set to 0.5ms, 2ms, or 4ms by the I²C. When the output voltage is shorted to GND, the feedback voltage is pulled low and VSS is discharged. The part soft starts again when it returns to its normal state.

Pre-Bias Start-Up

For this device, at start-up, if the output feedback voltage is greater than VSS, which means the output has pre-bias voltage, neither the HS-FET nor LS-FET turn on until VSS exceeds the feedback voltage.

Power Good Indicator

This device has power good (PG) indication. The PG pin is the open drain of a MOSFET. It should be connected to a voltage source through a resistor (e.g. 100kΩ). In the presence of an input voltage, the MOSFET turns on so that the PG pin is pulled to GND before soft start is ready. When the output voltage is within default ±10% window of the rated voltage, the PG pin is pulled high after a delay (typically 30μs).

If V_OUT moves outside the default ±10% range with a hysteresis, the device pulls PG low to indicate a failure output status. Both the PG threshold and hysteresis can be programmed by the I²C.

FAULT Indicator

The /FT pin is also an open drain of a MOSFET. It should be connected to a voltage source through a resistor (e.g. 100kΩ). The /FT pin is pulled high in normal operation, and any fault or warning pulls this pin low to indicate a fault status, including input OVP, output OVP, SCP, and thermal shutdown.

Over-Current Protection (OCP)

This device has cycle-by-cycle over-current limit control. The inductor current is monitored during the HS-FET on state. Once the inductor peak current exceeds the set current limit threshold, the HS-FET immediately turns off. Then the LS-FET turns on to discharge the energy, and the inductor current decreases. The HS-FET does not turn on again until the inductor current is below a certain current threshold, called the valley current limit. This prevents the inductor current from running away and possibly damaging the components. Both the peak current and valley current threshold can be programmed by the I²C.

When the peak current limit is triggered, the OCP timer starts immediately. The OCP timer can be set to 32, 64, 128, or 256 cycles by the I²C. Reaching the current limit during each cycle during this OCP timer triggers SCP operation (hiccup as default), which is introduced in the following section.

Short-Circuit Protection (SCP)

When a short circuit occurs, this device immediately reaches its current limit. Meanwhile, the output voltage quickly drops to its under-voltage threshold¬ (default is 50% of the setting output). The device considers this an output dead short and directly triggers SCP operation. Three modes can be selected by the I²C for SCP operation: hiccup as default, switching with non-hiccup, and latch-off.

In default hiccup mode, this device disables its output power stage and resets the soft-start voltage, then initiates a soft start. The off time is determined by the soft-start time and hiccup duty, which can both be set by the I²C. If the short-circuit condition still remains after soft start ends, the device repeats this operation until the short circuit disappears and the output returns to the regulation level. This protection mode greatly reduces the average short-circuit current by periodically restarting the part to alleviate thermal issues and protect the regulator.

Output Over-Voltage Protection (V_OUT OVP)

This device monitors the output voltage through the V_OUT pin to detect output over-voltage conditions. When the output voltage exceeds OVP threshold (the default is 120% of the setting voltage), OVP mode is triggered. Three modes can be selected by the I²C for OVP operation: disable as default, discharge, and latch-off.

Input Over-Voltage Protection (V_IN OVP)

This device also has optional input OVP. The threshold can be set to 28V, 34V, or 40V. If V_IN exceeds the threshold, the device stops switching. This is a non-latch protection, and there is a hysteresis of either 2.5% or 5% of the input OVP threshold voltage. The device resumes normal operation when the input OVP is removed. Both the input OVP threshold and hysteresis can be set by the I²C interface.

Thermal Shutdown

This device has over-temperature protection (OTP) by monitoring the IC temperature internally. This function prevents the chip from operating at exceedingly high temperatures. If the junction temperature exceeds the threshold (default 175°C), it shuts down the whole chip. This is a non-latch protection, and there is a default 25°C hysteresis. Once the junction temperature drops to about 150°C, the device resumes operation by initiating a soft start. Both the OTP threshold and hysteresis can be set by the I²C interface.

Floating Driver and Bootstrap Charging

An external bootstrap capacitor powers the floating power MOSFET driver. The floating driver has its own UVLO protection, with a rising threshold of 2.5V and hysteresis of 200mV.

The bootstrap capacitor voltage is charged to about 5V from VCC through a PMOS pass transistor when the LS-FET is on.

In high duty cycle operation or sleep mode, the bootstrap charging time period is shorter, so the bootstrap capacitor may not be charged sufficiently. In case the external circuit does not have sufficient voltage and time to charge the bootstrap capacitor, extra external circuitry can be used to ensure the bootstrap voltage is in the normal operation range.

Low-Dropout Operation (BST Refresh)

To improve dropout, the device is designed to operate at close to 100% duty cycle as long as the BST to SW pin voltage is greater than 2.5V. When the voltage from BST to SW drops below 2.5V, the high-side MOSFET turns off using a UVLO circuit that allows the low-side MOSFET to conduct and refresh the charge on the BST capacitor.

In cases where the input voltage drops, the HS-FET remains on and close to 100% duty cycle to maintain output regulation, until the BST to SW voltage falls below 2.5V. Since the supply current sourced from the BST capacitor is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor. Therefore, the effective duty cycle of the switching regulator is high.

The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode, and PCB resistance.

I²C Control and Default Output Voltage

When the device is enabled (which means EN = high and V_IN > UVLO), the chip starts up to a default 5V output voltage. After that, the I²C bus can communicate with master. Once the I²C receives a valid output voltage set instruction, the output voltage is determined by the I²C control.

The output voltage is set by adjusting the internal reference voltage and output feedback divider ratio. After this device receives a valid data byte of output voltage setting, it searches the corresponding value from the truth table and then sends the command of adjusting reference and divider ratio. Finally, it outputs the correct voltage.

Frequency Dithering for Low EMI

Frequency dithering is a technique used in the power industry to reduce EMI, especially for EMI-sensitive applications. This spread-spectrum modulation technique spreads the frequency spectrum of converter, which in turn spreads the energy of the switching harmonics over a wider band while reducing their amplitudes, helping to meet stringent EMI goals

The programmable frequency dithering feature of this device allows either 3/48 or 3/28 variation range in the switching frequency, with a 120µs or 150µs dithering cycle. Both the frequency dithering range and cycle can be set by the I²C interface.

Multi-Page One-Time-Programmable Memory

The device features three pages of one-time-programmable memory to store desired settings permanently.

Differential one-time-programmable cells, rather than single-ended, are used for long-term reliability. Data is stored on two floating gate avalanche injection metal oxide semiconductor (FAMOS), and output comparators are used for differential reading.

The first page of the multi-page one-time-programmable memory has been programmed with manufacturer default values.

Once the device is enabled, the default values on the first page are used to set the control parameters in the registers. If there is data on other pages of the one-time-programmable memory, the newest setting is identified by an internal indicator to write registers. See the Register Map and Register Description sections for details.